Fast growth of the pervasive computing and handheld/communication industry generates exploding demand for high capacity nonvolatile solid-state data storage devices. It is believed that nonvolatile memories, especially flash memory, will replace DRAM to occupy the biggest share of memory market by 2009. However, flash memory has several drawbacks such as slow access speed (˜ms write and ˜50-100 ns read), limited endurance (˜103-104 programming cycles), and the integration difficulty in system-on-chip (SoC). Flash memory (NAND or NOR) also faces significant scaling problems at 32 nm node and beyond.
Magneto-resistive Random Access Memory (MRAM) is another promising candidate for future nonvolatile and universal memory. MRAM features non-volatility, fast writing/reading speed (<10 ns), almost unlimited programming endurance (>1015 cycles) and zero standby power. The basic component of MRAM is a magnetic tunneling junction (MTJ). Data storage is realized by switching the resistance of MTJ between a high-resistance state and a low-resistance state. MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ. As the MTJ size shrinks, the switching magnetic field amplitude increases and the switching variation becomes severer. Hence, the incurred high power consumption limits the scaling of conventional MRAM.
Recently, a new write mechanism, which is based upon spin polarization current induced magnetization switching, was introduced to the MRAM design. This new MRAM design, called Spin-Transfer Torque RAM (STRAM), uses a (bidirectional) current through the MTJ to realize the resistance switching. Therefore, the switching mechanism of STRAM is constrained locally and STRAM is believed to have a better scaling property than the conventional MRAM.
However, a number of yield-limiting factors must be overcome before STRAM enters the production stage. A positive current (i.e., electrons flow from the pinned layer to the free layer of the MTJ) must be used to program the cell into the low resistance mode. On the other hand, a negative current (i.e., electrons flow from the free layer to the pinned layer of the MTJ) is necessary to switch the magnetization state back to antiparallel (high resistance mode). Because of the requirement of a bipolar current in the write mode, a metal-oxide-semiconductor field effect transistor (MOSFET) is needed in the memory cell design. Due to the large critical switching current, the lateral size of MOSFET needs to be large to provide enough drive current, which causes problems in scaling and is a barrier for higher density integration. Furthermore, this design requires three contact terminals: a bit line, a gate contact (or word line), and a source contact.